High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices by stacking dies vertically and interconnecting the dies using through-silicon vias (TSVs) have been introduced. Benefits of the 3D memory devices include a plurality of dies stacked with a large number of vertical vias between the plurality of dies and memory controller, which allow wide bandwidth buses with high transfer rates between functional blocks in the plurality of dies, and a considerably smaller footprint. Thus, the 3D memory devices contribute to large memory capacity, higher memory access speed and chip size reduction. The 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
In the 3D memory devices above, the plurality of dies connected using through silicon vias (TSVs) are in Master-Slave (MS) configuration. A master die (MD) (e.g., an interface die) receives commands and data from a system, and transmits the commands and the data to a destination die. The destination die may be the master die itself or one of a plurality of slave dies (SDs) (e.g., a plurality of core dies) based on a chip identifier indicating the destination die that is received along with the command.
Each die of the master die and the plurality of the slave dies may generate internal state information. For example, the internal state information may indicate an active state of a die when a bank associated with the die is activated and any external load mode register command is configured to be ignored. Another example is when the internal state information may indicate an active state of the die responsive to a command, such as a read command, write command, or auto pre-charge command, associated with the die is issued and the master die needs to keep providing its clock signal regardless of the internal state of the master die. FIG. 1A is a schematic diagram of a conventional semiconductor device including through-silicon vias (TSVs) in a plurality of dies. The conventional semiconductor device 1 may include a plurality of dies 2a to 2h including a master die 2a and seven slave dies 2b to 2h. For example, the number of the plurality of dies in FIG. 1A may be eight, however the number of the plurality of dies is not limited to eight. The internal state information of each die is transmitted to the master die 2a using the TSVs. Each slave die transmits its one bit internal state information, and a plurality of TSVs including one TSV to transmit one bit internal state information for each die (e.g., eight TSV0 of eight dies, . . . , or eight TSV7 of the eight dies) are included in a path.
Each die has a state information transmitter (e.g., a master state information generator 3a, slave state information generators 3b to 3h) that generates a state bit signal (StateBit). FIG. 1B is a conventional state information generator 3 in the semiconductor device 1. The conventional state information generator 3 may be the master state information generator 3a, and/or the slave state information generators 3b to 3h. A NAND circuit receives the active StateBit signal based on a command and an enable signal en and provides a “logic low” signal to a gate of a P-channel field effect transistor to set (e.g., pull up) a first voltage (e.g., a positive power supply) an output signal of the conventional state information generator 3 when a StateBit signal is active, and a NOR circuit receives inactive StateBit signal based on the command and an inverted enable signal enF and provides a “logic high” signal to a gate of an N-channel field effect transistor to set (e.g., pull down) the output signal of the conventional state information generator 3 to a second voltage (e.g., a ground level or a negative power supply voltage). Thus, the conventional state information generator 3 provides the output signal having the logic high level or the logic low level, responsive to an active StateBit signal or the inactive StateBit signal, respectively. Because each die has the conventional state information generator 3 (e.g., a master state information generator 3a, slave state information generators 3b to 3h in FIG. 1B) that generates a StateBit signal indicating its internal state information and a dedicated path to transmit the StateBit signal, a plurality of paths, including a path including a plurality of TSV0s of the plurality of corresponding dies (e.g., “x” representing a number of the plurality of dies), . . . , a path including a plurality of TSVys of the plurality of corresponding dies (e.g., a number “y” representing a number of state bit signals), are included in the conventional semiconductor device 1.
The conventional semiconductor device 1 further includes a global state information generator 4 in the master die 2a. The global state information generator 4 receives the StateBit signals on the eight paths from the dies 2a to 2h and generates a StateBitGlobal signal. FIG. 1C is a timing diagram of signals related to state information of dies of FIG. 1A. For example, the signals may be the StateBit signals of dies 2a and 2b of FIG. 1A. The StateBitGlobal signal is a logical sum of the StateBit signals from the dies 2a and 2b. Thus, the StateBigGlobal signal indicates that at least one die of the plurality of dies is active responsive to any of the StateBit signals from the plurality of dies indicating that a corresponding die is active.
In order to receive the internal state information for each die, a number of TSVs in each path is a number of the state bit signals “y” and a number of paths is a number of the plurality of dies “x”. When the number of the plurality of dies “x” increases, the total number of TSVs “x*y” in the semiconductor device increases. If the number of dies increases to 16, 32, . . . , the number of TSVs to be included will be substantially large which prohibits size reduction of the footprint of the semiconductor device.